sci-electronics/iverilog (gentoo)

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Package Information

Description:
Icarus Verilog is a Verilog simulation and synthesis tool. It operates as a compiler, compiling source code writen in Verilog (IEEE-1364) into some target format. The compiler proper is intended to parse and elaborate design descriptions written to the IEEE standard IEEE Std 1364-2001.
Homepage:
http://iverilog.icarus.com https://github.com/steveicarus/iverilog

Versions

Version EAPI Keywords Slot
9999 8 ~amd64 ~arm ~arm64 ~ppc ~ppc64 ~riscv ~x86 0
12.0 8 amd64 ~arm ~arm64 ~ppc ~ppc64 ~riscv ~x86 0
11.0 7 amd64 ~arm ~arm64 ~ppc ~ppc64 ~riscv ~x86 0
10.3 8 amd64 ~arm ~arm64 ~ppc ~ppc64 ~riscv ~x86 0

Metadata

Description

Maintainers

Upstream

Raw Metadata XML
<pkgmetadata>
	<maintainer type="person" proxied="yes">
		<email>vowstar@gmail.com</email>
		<name>Huang Rui</name>
	</maintainer>
	<maintainer type="project">
		<email>sci-electronics@gentoo.org</email>
		<name>Gentoo Electronics Project</name>
	</maintainer>
	<maintainer type="project" proxied="proxy">
		<email>proxy-maint@gentoo.org</email>
		<name>Proxy Maintainers</name>
	</maintainer>
	<longdescription>
	Icarus Verilog is a Verilog simulation and synthesis tool. It operates as a
	compiler, compiling source code writen in Verilog (IEEE-1364) into some target
	format. The compiler proper is intended to parse and elaborate design
	descriptions written to the IEEE standard IEEE Std 1364-2001.
	</longdescription>
	<upstream>
		<remote-id type="github">steveicarus/iverilog</remote-id>
	</upstream>
</pkgmetadata>

Lint Warnings

USE Flags

Flag Description 9999 12.0 11.0 10.3
examples Install examples, usually source code

Files

Manifest

Type File Size Versions
DIST iverilog-10.3.tar.gz 1600835 bytes 10.3
DIST iverilog-11.0.tar.gz 1682457 bytes 11.0
DIST iverilog-12.0.tar.gz 2995096 bytes 12.0
Unmatched Entries
Type File Size