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Install

Install this package:

emerge -a sci-electronics/iverilog

If the package is masked, you can unmask it using the autounmask tool or standard emerge options:

autounmask sci-electronics/iverilog

Or alternatively:

emerge --autounmask-write -a sci-electronics/iverilog

Package Information

Description:

Icarus Verilog is a Verilog simulation and synthesis tool. It operates as a compiler, compiling source code writen in Verilog (IEEE-1364) into some target format. The compiler proper is intended to parse and elaborate design descriptions written to the IEEE standard IEEE Std 1364-2001.

Homepage:

http://iverilog.icarus.com https://github.com/steveicarus/iverilog

License:

GPL-2+

Versions

Metadata

Description

• Icarus Verilog is a Verilog simulation and synthesis tool. It operates as a compiler, compiling source code writen in Verilog (IEEE-1364) into some target format. The compiler proper is intended to parse and elaborate design descriptions written to the IEEE standard IEEE Std 1364-2001.

Maintainers

• Huang Rui (vowstar@gmail.com) - Type: person
• Gentoo Electronics Project (sci-electronics@gentoo.org) - Type: project
• Proxy Maintainers (proxy-maint@gentoo.org) - Type: project

Upstream

• Remote IDs:
  • github: steveicarus/iverilog

<pkgmetadata>
	<maintainer type="person" proxied="yes">
		<email>vowstar@gmail.com</email>
		<name>Huang Rui</name>
	</maintainer>
	<maintainer type="project">
		<email>sci-electronics@gentoo.org</email>
		<name>Gentoo Electronics Project</name>
	</maintainer>
	<maintainer type="project" proxied="proxy">
		<email>proxy-maint@gentoo.org</email>
		<name>Proxy Maintainers</name>
	</maintainer>
	<longdescription>
	Icarus Verilog is a Verilog simulation and synthesis tool. It operates as a
	compiler, compiling source code writen in Verilog (IEEE-1364) into some target
	format. The compiler proper is intended to parse and elaborate design
	descriptions written to the IEEE standard IEEE Std 1364-2001.
	</longdescription>
	<upstream>
		<remote-id type="github">steveicarus/iverilog</remote-id>
	</upstream>
</pkgmetadata>

Lint Warnings

• [Warning] USE flag 'examples' in ebuild 10.3 is not documented in metadata.xml
• [Error] Missing md5-cache for ebuild iverilog-9999
• [Error] Missing md5-cache for ebuild iverilog-12.0
• [Error] Missing md5-cache for ebuild iverilog-11.0
• [Error] Missing md5-cache for ebuild iverilog-10.3

USE Flags

Manage flags for this package: euse -i <flag> -p sci-electronics/iverilog | euse -E <flag> -p sci-electronics/iverilog | euse -D <flag> -p sci-electronics/iverilog

Files

• iverilog-10.3-call-nm.patch
• iverilog-10.3-configure-ac.patch
• iverilog-10.3-file-missing.patch
• iverilog-10.3-fno-common.patch
• iverilog-10.3-gen-bison-header.patch
• iverilog-10.3-override-var.patch
• iverilog-11.0-autoconf-2.70.patch

Manifest