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Description:

NVC is a VHDL compiler and simulator. NVC supports almost all of VHDL-2008 with the exception of PSL, and it has been successfully used to simulate several real-world designs. Experimental support for VHDL-2019 is under development. NVC has a particular emphasis on simulation performance and uses LLVM to compile VHDL to native machine code. NVC is not a synthesizer. That is, it does not output something that could be used to program an FPGA or ASIC. It implements only the simulation behaviour of the language as described by the IEEE 1076 standard. NVC supports popular verification frameworks including OSVVM, UVVM, and VUnit.

Homepage:

https://www.nickg.me.uk/nvc/ https://github.com/nickg/nvc/

License:

GPL-3+

Versions

Metadata

Description

• NVC is a VHDL compiler and simulator. NVC supports almost all of VHDL-2008 with the exception of PSL, and it has been successfully used to simulate several real-world designs. Experimental support for VHDL-2019 is under development. NVC has a particular emphasis on simulation performance and uses LLVM to compile VHDL to native machine code. NVC is not a synthesizer. That is, it does not output something that could be used to program an FPGA or ASIC. It implements only the simulation behaviour of the language as described by the IEEE 1076 standard. NVC supports popular verification frameworks including OSVVM, UVVM, and VUnit.

Maintainers

• Maciej Barć (xgqt@gentoo.org) - Type: person

Upstream

• Bugs: https://github.com/nickg/nvc/issues/
• Remote IDs:
  • github: nickg/nvc
  • sourcehut: ~nickg/nvc

<pkgmetadata>
	<maintainer type="person">
		<email>xgqt@gentoo.org</email>
		<name>Maciej Barć</name>
	</maintainer>
	<longdescription>
    NVC is a VHDL compiler and simulator. NVC supports almost all of VHDL-2008
    with the exception of PSL, and it has been successfully used to simulate
    several real-world designs. Experimental support for VHDL-2019 is under
    development. NVC has a particular emphasis on simulation performance and
    uses LLVM to compile VHDL to native machine code. NVC is not a synthesizer.
    That is, it does not output something that could be used to program an FPGA
    or ASIC. It implements only the simulation behaviour of the language as
    described by the IEEE 1076 standard. NVC supports popular verification
    frameworks including OSVVM, UVVM, and VUnit.
  </longdescription>
	<use>
		<flag name="llvm">Build LLVM code generator</flag>
	</use>
	<upstream>
		<bugs-to>https://github.com/nickg/nvc/issues/</bugs-to>
		<remote-id type="github">nickg/nvc</remote-id>
		<remote-id type="sourcehut">~nickg/nvc</remote-id>
	</upstream>
</pkgmetadata>

Lint Warnings

• [Warning] Missing md5-cache for version 1.19.3. Run 'ebuild <ebuild_file> manifest' or 'egencache' to generate it.
• [Warning] Missing md5-cache for version 1.19.2. Run 'ebuild <ebuild_file> manifest' or 'egencache' to generate it.
• [Warning] Missing md5-cache for version 1.18.2-r1. Run 'ebuild <ebuild_file> manifest' or 'egencache' to generate it.

USE Flags

Files

• nvc-1.9.2-jit-code-capstone.patch

Manifest