sci-electronics/bender::vowstar
- Ebuilds: 1, Testing: 0.32.1 Description:
Bender is a dependency management tool for hardware design projects.
It provides a way to define dependencies among IPs, execute unit tests,
and verify that the source files are valid input for various simulation
and synthesis tools.
Homepage:https://github.com/pulp-platform/bender License: || ( Apache-2.0 MIT ) Apache-2.0 BSD ISC MIT MPL-2.0 Unicode-3.0 ZLIB
sci-electronics/bluespec::vowstar
- Ebuilds: 5, Testing: 2026.01, Snapshot: 9999 Description:
This is a compiler, simulator, and associated tools for Bluespec High
Level Hardware Design Language (HL-HDL), supporting the two optional
syntaxes, BSV and BH. Language specifications and tutorials are
available in the BSVlang repository.
Bluespec is a high-level hardware description language. It has a variety
of advanced features including a powerful type system that can prevent
errors prior to synthesis time, and its most distinguishing feature,
Guarded Atomic Actions, allow you to define hardware components in a
modular manner based on their invariants, and let the compiler pick a
scheduler.
Homepage:https://github.com/B-Lang-org/bsc License: BSD GPL-3+ MIT
sci-electronics/circt::vowstar
- Ebuilds: 1, Testing: 1.159.0 Description:
CIRCT is an umbrella project containing reusable compiler
infrastructure for hardware design tools. It provides hardware
intermediate representations, transformations, and command-line tools
built on LLVM and MLIR.
Homepage:
https://circt.llvm.org
https://github.com/llvm/circt
License: Apache-2.0-with-LLVM-exceptions UoI-NCSA BSD public-domain rc
sci-electronics/cocotb::vowstar
- Ebuilds: 3, Testing: 2.1.0 Description:
cocotb is an open source coroutine-based cosimulation testbench
environment for verifying VHDL and SystemVerilog RTL using Python.
It allows you to write testbenches in Python and interface with
simulators like Icarus Verilog, GHDL, VCS, ModelSim, Questa and
others to verify hardware designs.
Homepage:https://www.cocotb.org License: BSD
sci-electronics/cocotb-bus::vowstar
- Ebuilds: 1, Testing: 0.3.0 Description:
cocotb-bus provides pre-packaged testbenching tools and reusable bus
interfaces for the cocotb project. It helps with verification of
digital designs by providing ready-to-use bus protocol implementations
and utilities to make testing hardware easier.
Homepage:https://github.com/cocotb/cocotb-bus License: BSD
sci-electronics/coil64::vowstar
- Ebuilds: 1, Testing: 2.4.39 Description:
Coil64 is inductance coil calculator, that allows to calculate the
single-layer and multi-layer air core inductors, the ferrite toroid
inductors or chokes, flat square coils on PCB etc.
You can help to translate application by the Crowdin Coil64 project.
Homepage:
https://coil32.net
https://github.com/radioacoustick/Coil64
License: GPL-3
sci-electronics/digilent-adept-runtime::vowstar
- Ebuilds: 1, Testing: 2.27.9 Description:
The Adept Runtime consists of the shared libraries, firmware images, and
configuration files necessary to communicate with Digilent's devices.
Features:
Configure Xilinx® logic devices. Initialize a scan chain, program FPGAs,
CPLDs, and PROMs, organize and keep track of your configuration files.
Transfer data to and from the onboard FPGA on your system board. Read from
and write to specified registers. Load a stream of data to a register or
read a stream of data from a register.
Organize and quickly connect to your communications modules.
Program Xilinx XCFS Platform Flash devices using .bit or .mcs files.
Program Xilinx CoolRunner2 CPLDs using .jed files.
Program most Spartan and Virtex series FPGAs with .bit files.
Homepage:https://digilent.com/shop/software/digilent-adept License: all-rights-reserved
sci-electronics/digilent-adept-utilities::vowstar
- Ebuilds: 1, Testing: 2.7.1 Description:
Digilent Adept is a unique and powerful solution which allows you to
communicate with Digilent system boards and a wide assortment of logic
devices.
Features:
Configure Xilinx® logic devices. Initialize a scan chain, program FPGAs,
CPLDs, and PROMs, organize and keep track of your configuration files.
Transfer data to and from the onboard FPGA on your system board. Read from
and write to specified registers. Load a stream of data to a register or
read a stream of data from a register.
Organize and quickly connect to your communications modules.
Program Xilinx XCFS Platform Flash devices using .bit or .mcs files.
Program Xilinx CoolRunner2 CPLDs using .jed files.
Program most Spartan and Virtex series FPGAs with .bit files.
Homepage:https://digilent.com/shop/software/digilent-adept License: all-rights-reserved
sci-electronics/dsview::vowstar
- Ebuilds: 2, Testing: 1.3.2, Snapshot: 9999 Description:
DSView is an GUI programe for supporting various instruments from
DreamSourceLab, including logic analyzer, oscilloscope, etc. DSView is based
on sigrok project.
The sigrok project aims at creating a portable, cross-platform,
Free/Libre/Open-Source signal analysis software suite that supports various
device types (such as logic analyzers, oscilloscopes, multimeters, and
more).
Homepage:
https://www.dreamsourcelab.com
https://github.com/DreamSourceLab/DSView
License: GPL-3
sci-electronics/jlc-assistant-bin::vowstar
- Ebuilds: 1, Testing: 5.0.69 Description:
JLC Order Assistant: This app provides convenience for you to place an
order, and quickly obtain discounts and order information, without waiting
for review on the website! Place an order in the order assistant and enjoy
a discount immediately!
Homepage:https://www.jlc.com/portal/appDownloadsWithConfig.html License: all-rights-reserved
sci-electronics/kicad::vowstar
- Ebuilds: 5, Stable: 10.0.3, Testing: 10.0.5, Snapshot: 9999 Description:
Kicad is an open source (GPL) software for the creation of electronic
schematic diagrams and printed circuit board artwork.
Homepage:https://www.kicad.org License: GPL-2+ GPL-3+ Boost-1.0 BSD BSD-2 Apache-2.0 ISC MIT ZLIB CC-BY-SA-4.0 CC0-1.0 WTFPL-2
sci-electronics/kicad-footprints::vowstar
- Ebuilds: 5, Stable: 10.0.3, Testing: 10.0.5, Snapshot: 9999 Description:
The KiCad footprint libraries are the individual .pretty directories.
Each .pretty directory contains multiple .kicad_mod footprint files.
These footprints are best used in combination with the official symbol
libs and 3d model libs.
Homepage:https://gitlab.com/kicad/libraries/kicad-footprints License: CC-BY-SA-4.0
sci-electronics/kicad-packages3d::vowstar
- Ebuilds: 5, Stable: 10.0.3, Testing: 10.0.5, Snapshot: 9999 Description:
The KiCad 3D model libraries are the individual .3dshapes directories.
These 3d models are best used in combination with the official footprint
libs. Each directory directory contains multiple 3D model files, with
the following supported file formats: WRL, STEP.
Homepage:https://gitlab.com/kicad/libraries/kicad-packages3D License: CC-BY-SA-4.0
sci-electronics/openems::vowstar
- Ebuilds: 1, Testing: 0.0.36 Description:
openEMS is a free and open electromagnetic field solver using the
FDTD method. It supports Cartesian and cylindrical coordinates,
multi-threading via OpenMP, SIMD acceleration, and a Matlab/Octave
scripting interface for setting up simulations.
Homepage:https://openems.de https://github.com/thliebig/openEMS License: GPL-3
sci-electronics/opensta::vowstar
- Ebuilds: 1, Testing: 2.7.0_pre20251212 Description:
OpenSTA is a gate level static timing verifier. As a stand-alone
executable it can be used to verify the timing of a design using
standard file formats. OpenSTA uses a TCL command interpreter to
read the design, specify timing constraints and print timing reports.
Homepage:https://github.com/parallaxsw/OpenSTA License: GPL-3
sci-electronics/plecs-bin::vowstar
- Ebuilds: 1, Testing: 5.0.3 Description:
PLECS Standalone is a block diagram simulator developed by Plexim
for high-speed simulations of power electronic circuits and
electrical systems. It combines an intuitive schematic editor
with a powerful simulation engine and provides specialized
libraries for power semiconductors, electrical machines, thermal
modeling and control. This package installs the proprietary
Linux 64-bit binary distribution; a valid license from Plexim is
required at runtime.
Homepage:https://www.plexim.com/products/plecs/plecs_standalone License: Plexim-EULA
sci-electronics/sby::vowstar
- Ebuilds: 1, Testing: 0.69 Description:
SymbiYosys (sby) is a front-end driver program for Yosys-based formal
hardware verification flows. It supports bounded model checking (BMC),
unbounded model checking, and cover property checking for hardware
designs written in Verilog, SystemVerilog, or VHDL. SymbiYosys
integrates with various SMT solvers and model checkers including
Yices, Z3, Boolector, and ABC.
Homepage:https://github.com/YosysHQ/sby License: ISC
sci-electronics/slang::vowstar
- Ebuilds: 2, Testing: 11.0, Snapshot: 9999 Description:
slang is a software library that provides various components for lexing,
parsing, type checking, and elaborating SystemVerilog code. It comes with
an executable tool that can compile and lint any SystemVerilog project,
but it is also intended to be usable as a front end for synthesis tools,
simulators, linters, code editors, and refactoring tools.
slang is the fastest and most compliant SystemVerilog frontend
(according to the open source chipsalliance test suite).
Homepage:
https://sv-lang.com
https://github.com/MikePopoloski/slang
License: MIT
sci-electronics/surfer::vowstar
- Ebuilds: 1, Testing: 0.7.0 Description:
Surfer is a waveform viewer with a focus on a snappy usable interface,
and support for many waveform formats. It can be used to view waveforms
from digital design simulations (VCD, FST, GHW) and supports features
like signal search, markers, and annotations. Surfer also includes a
server component (surver) for remote waveform viewing.
Homepage:https://surfer-project.org/ https://gitlab.com/surfer-project/surfer License: EUPL-1.2
0BSD Apache-2.0 Apache-2.0-with-LLVM-exceptions BSD Boost-1.0
CC0-1.0 CDLA-Permissive-2.0 EUPL-1.2 ISC MIT MPL-2.0 OFL-1.1
UbuntuFontLicense-1.0 Unicode-3.0 ZLIB
sci-electronics/systemc::vowstar
- Ebuilds: 2, Stable: 2.3.4, Testing: 3.0.2 Description:
SystemC provides hardware-oriented constructs within the context of C++
as a class library implemented in standard C++. Its use spans design and
verification from concept to implementation in hardware and software.
SystemC provides an interoperable modeling platform which enables the
development and exchange of very fast system-level C++ models. It also
provides a stable platform for development of system-level tools.
Homepage:
https://systemc.org
https://github.com/accellera-official/systemc
License: Apache-2.0
sci-electronics/topola::vowstar
- Ebuilds: 1, Testing: 0.1.0_pre20251201 Description:
Topola is a work-in-progress interactive topological router for printed
circuit boards (PCBs) written in Rust. It implements rubberband-style
routing where traces behave like elastic bands wrapped around obstacles,
providing an intuitive way to route PCB traces interactively. The project
aims to provide both interactive routing and autorouting capabilities for
PCB design workflows.
Homepage:https://topola.dev https://codeberg.org/topola/topola License: MIT
Apache-2.0 Apache-2.0-with-LLVM-exceptions Boost-1.0 CC0-1.0 ISC MIT
MPL-2.0 OFL-1.1 UbuntuFontLicense-1.0 Unicode-3.0 ZLIB
sci-electronics/vcd::vowstar
- Ebuilds: 1, Testing: 221217 Description:
The VCD (Value Change Dump) project on GitHub is a command line viewer
for VCD files, compatible with Windows, Linux, and MacOS.
It enables users to view and analyze waveform data from digital
simulations. The tool provides customization options for waveform
display and supports various output formats including YAML.
Installation is available via prebuilt binaries, source compilation, or
package managers.
The project is actively maintained and includes sample files and
detailed usage instructions. The repository is licensed under MIT and
supports CLI operations for efficient waveform analysis.
Homepage:https://github.com/yne/vcd License: MIT
sci-electronics/verible::vowstar
- Ebuilds: 3, Testing: 0.0.3644 Description:
Verible is a suite of SystemVerilog developer tools, including a parser,
style-linter, and formatter.
The Verible project's main mission is to parse SystemVerilog
(IEEE 1800-2017) (as standardized in the SV-LRM) for a wide variety of
applications, including developer tools.
It was born out of a need to parse un-preprocessed source files, which is
suitable for single-file applications like style-linting and formatting.
In doing so, it can be adapted to parse preprocessed source files, which is
what real compilers and toolchains require.
The spirit of the project is that no-one should ever have to develop a
SystemVerilog parser for their own application, because developing a
standard-compliant parser is an enormous task due to the syntactic
complexity of the language. Verible's parser is also regularly tested
against an ever-growing suite of (tool-independent) language compliance
tests at https://symbiflow.github.io/sv-tests/.
A lesser (but notable) objective is that the language-agnostic components
of Verible be usable for rapidly developing language support tools for
other languages.
Homepage:
https://chipsalliance.github.io/verible/
https://github.com/chipsalliance/verible
License: Apache-2.0
sci-electronics/wavedrom-editor-bin::vowstar
- Ebuilds: 1, Testing: 2.9.1 Description:
WaveDromEditor is real-time editor of digital timing diagrams based on
WaveDrom engine and WaveJSON format. WaveDrom draws your Timing Diagram
or Waveform from simple textual description.
It comes with description language, rendering engine and the editor.
WaveDrom editor works in the browser or can be installed on your system.
Rendering engine can be embeded into any webpage.
Homepage:
https://wavedrom.com
https://github.com/wavedrom/wavedrom.github.io
License: MIT
sci-electronics/yosys::vowstar
- Ebuilds: 1, Testing: 0.69 Description:
This is a framework for RTL synthesis tools. It currently has extensive
Verilog-2005 support and provides a basic set of synthesis algorithms
for various application domains.
Yosys can be adapted to perform any synthesis job by combining the
existing passes (algorithms) using synthesis scripts and adding
additional passes as needed by extending the yosys C++ code base.
Yosys is free software licensed under the ISC license (a GPL compatible
license that is similar in terms to the MIT license or the 2-clause BSD
license).
Homepage:https://yosyshq.net/yosys/ License: ISC