sci-electronics/yosys (xdch47)

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Install

Install this package:

emerge -a sci-electronics/yosys

Package Information

Description:
framework for Verilog RTL synthesis
Homepage:
http://www.clifford.at/yosys/
License:
ISC

Versions

Version EAPI Keywords Slot
0.56 8 ~amd64 0

Metadata

Maintainers

Upstream

Raw Metadata XML
<pkgmetadata>
	<maintainer type="person">
		<email>xdch47@posteo.de</email>
		<name>Felix Neumärker</name>
	</maintainer>
	<use>
		<flag name="clang">Use Clang compiler instead of GCC</flag>
		<flag name="abc">Use berkeley-abc (as yosys-abc) for technology mapping</flag>
	</use>
	<upstream>
		<remote-id type="github">YosysHQ/yosys</remote-id>
	</upstream>
</pkgmetadata>

Lint Warnings

USE Flags

Manage flags for this package: euse -i <flag> -p sci-electronics/yosys | euse -E <flag> -p sci-electronics/yosys | euse -D <flag> -p sci-electronics/yosys

Flag Description 0.56
abc Use berkeley-abc (as yosys-abc) for technology mapping
clang Use Clang compiler instead of GCC
libedit ⚠️
libffi ⚠️
python ⚠️
readline ⚠️