bender (available in: sci-electronics/bender::guru, sci-electronics/bender::vowstar)
- Ebuilds: 2, Testing: 0.32.1 Description:
Bender is a dependency management tool for hardware design projects.
It provides a way to define dependencies among IPs, execute unit tests,
and verify that the source files are valid input for various simulation
and synthesis tools.
Homepage:https://github.com/pulp-platform/bender License: || ( Apache-2.0 MIT ) Apache-2.0 BSD ISC MIT MPL-2.0 Unicode-3.0 ZLIB
bluespec (available in: sci-electronics/bluespec::guru, sci-electronics/bluespec::vowstar)
- Ebuilds: 10, Testing: 2026.01, Snapshot: 9999 Description:
This is a compiler, simulator, and associated tools for Bluespec High
Level Hardware Design Language (HL-HDL), supporting the two optional
syntaxes, BSV and BH. Language specifications and tutorials are
available in the BSVlang repository.
Bluespec is a high-level hardware description language. It has a variety
of advanced features including a powerful type system that can prevent
errors prior to synthesis time, and its most distinguishing feature,
Guarded Atomic Actions, allow you to define hardware components in a
modular manner based on their invariants, and let the compiler pick a
scheduler.
Homepage:https://github.com/B-Lang-org/bsc License: BSD GPL-3+ MIT
cocotb (available in: sci-electronics/cocotb::guru, sci-electronics/cocotb::vowstar)
- Ebuilds: 5, Testing: 2.1.0 Description:
cocotb is an open source coroutine-based cosimulation testbench
environment for verifying VHDL and SystemVerilog RTL using Python.
It allows you to write testbenches in Python and interface with
simulators like Icarus Verilog, GHDL, VCS, ModelSim, Questa and
others to verify hardware designs.
Homepage:https://www.cocotb.org License: BSD
dsview (available in: sci-electronics/dsview::guru, sci-electronics/dsview::vowstar)
- Ebuilds: 4, Testing: 1.3.2, Snapshot: 9999 Description:
DSView is an GUI programe for supporting various instruments from
DreamSourceLab, including logic analyzer, oscilloscope, etc. DSView is based
on sigrok project.
The sigrok project aims at creating a portable, cross-platform,
Free/Libre/Open-Source signal analysis software suite that supports various
device types (such as logic analyzers, oscilloscopes, multimeters, and
more).
Homepage:
https://www.dreamsourcelab.com
https://github.com/DreamSourceLab/DSView
License: GPL-3
sci-electronics/electric::gentoo
- Ebuilds: 1, Testing: 9.07 Description:
The Electric VLSI Design System is a complete Electronic Design Automation
(EDA) system that can handle many forms of circuit design, including:
* Custom IC layout
* Schematic Capture (digital and analog)
* Textual Languages such as VHDL and Verilog
* Programmable logic (FPGAs)
* ...and much more.
Homepage:https://www.gnu.org/software/electric/electric.html License: GPL-3+
sci-electronics/electronics-menu::gentoo
- Ebuilds: 1, Stable: 1.0, Testing: 1.0 Description:
Create a dedicated "Electronics" entry in the top-menu of your XDG-compliant
Desktop Environment (Gnome, KDE, etc...), so that you electronics
applications don't get stuck in "Education" anymore.
Homepage:http://www.gpleda.org/ License: GPL-2
sci-electronics/flexbv-free-bin::guru
- Ebuilds: 2, Testing: 5.3162 Description:
FlexBV Free edition is a slimmed down product of the full licenced version.
It's a modern and cross platform alternative to existing boardview programs.
Homepage:https://pldaniels.com/flexbv5/ License: FlexBV-Free-EULA
sci-electronics/geda::gentoo
- Ebuilds: 1, Stable: 1.10.2, Testing: 1.10.2 Description:
The GPL Electronic Design Automation (gEDA) project has produced and
continues working on a full GPL'd suite and toolkit of Electronic
Design Automation tools. These tools are used for electrical circuit
design, schematic capture, simulation, prototyping, and
production. Currently, the gEDA project offers a mature suite of free
software applications for electronics design, including schematic
capture, attribute management, bill of materials (BOM) generation,
netlisting into over 20 netlist formats, analog and digital
simulation, and printed circuit board (PCB) layout.
The gEDA/gaf suite (this package) provides schematic capture,
netlisting, bill of materials generation, and many other features.
Homepage:http://geda-project.org/ http://wiki.geda-project.org/geda:gaf License: GPL-2
sci-electronics/gerbv::gentoo
- Ebuilds: 2, Stable: 2.7.0, Testing: 2.13.0 Description:
Gerbv is a viewer for Gerber RS-274X files, Excellon drill files, and CSV
pick-and-place files. (Note: RS-274D files are not supported.)
The core functionality of gerbv is located in a separate library
(libgerbv), allowing developers to include Gerber
parsing/editing/exporting/rendering into other programs.
Homepage:http://gerbv.geda-project.org/ License: GPL-2
sci-electronics/ghdl::gentoo
- Ebuilds: 1, Stable: 6.0.0, Testing: 6.0.0 Description:
GHDL is a shorthand for G Hardware Design Language (currently, G has no
meaning). It is a VHDL analyzer, compiler, simulator and (experimental)
synthesizer that can process (nearly) any VHDL design. Unlike some other
simulators, GHDL is a compiler: it directly translates a VHDL file to
machine code, without using an intermediary language such as C or C++.
Therefore, the compiled code should be faster and the analysis time should
be shorter than with a compiler using an intermediary language. GHDL can
use multiple back-ends, i.e. code generators, (GCC, LLVM or x86/i386 only,
a built-in one named mcode) and runs on GNU/Linux, Windows and macOS; on
x86, x86_64, armv6/armv7/aarch32/aarch64, ppc64, etc. GHDL aims at
implementing VHDL as defined by IEEE 1076. It supports the 1987, 1993 and
2002 revisions and, partially, 2008 and 2019. Property Specification
Language (PSL) is also partially supported.
Homepage:https://ghdl.github.io/ghdl/
https://github.com/ghdl/ghdl/ License: GPL-2+
sci-electronics/gnetman::gentoo
- Ebuilds: 1, Testing: 0.0.1_pre20110124 Description:
The gnetman project has one simple goal: Enabling interoperability between
open-source EDA tools. To date, gnetman can read and/or write (in theory)
formats used by the following tools :
* gschem
* iverilog
* ltspice, hspice, eldo, gnucap, tclspice
* confluence
Homepage:https://sourceforge.net/projects/gnetman/ License: GPL-2
sci-electronics/gnucap::gentoo
- Ebuilds: 1, Stable: 20210107, Testing: 20210107 Description:
Gnucap is a general purpose circuit simulator. It performs nonlinear dc and
transient analyses, fourier analysis, and ac analysis. Gnucap is not based on
Spice, but some of the models have been derived from the Berkeley models.
Unlike Spice, the engine is designed to do true mixed-mode simulation. Most
of the code is in place for future support of event driven analog simulation,
and true multi-rate simulation.
Homepage:http://www.gnucap.org/ License: GPL-2
sci-electronics/gtkwave::gentoo
- Ebuilds: 1, Stable: 3.3.125, Testing: 3.3.125 Description:
GTKWave is a fully featured GTK+ based wave viewer for Unix and Win32 which
reads LXT, LXT2, VZT, and GHW files as well as standard Verilog VCD/EVCD
files and allows their viewing.
Homepage:https://gtkwave.github.io/gtkwave/ License: GPL-2+ MIT
sci-electronics/gwave::gentoo
- Ebuilds: 1, Stable: 20190116, Testing: 20190116 Description:
Gwave is a waveform viewer. Gwave can read binary or ascii files written by
HSpice from transient, AC, or Sweep analyses, "raw" files written by Spice2,
Spice3, or ngspice, and transient analysis files from the CAzM simulator. It
can also read a generic tabular ASCII format suitable for use with GnuCap or
homegrown tools.
Homepage:http://gwave.sourceforge.net License: GPL-2
sci-electronics/irsim::gentoo
- Ebuilds: 2, Testing: 9.7.93 Description:
IRSIM is a tool for simulating digital circuits. It is a "switch-level"
simulator; that is, it treats transistors as ideal switches. Extracted
capacitance and lumped resistance values are used to make the switch a
little bit more realistic than the ideal, using the RC time constants
to predict the relative timing of events.
Homepage:http://opencircuitdesign.com/irsim/ License: GPL-2
sci-electronics/lceda::gentoo-zh
- Ebuilds: 1, Testing: 6.5.51 Description:
Simple and efficient PCB design tools from China, free forever
Friendly, easy to use, powerful, multi-platform synchronization
More than one million free libraries,
allowing you to focus more on design
The next generation of free domestic circuit design tools
Homepage:https://lceda.cn/ License: LCEDA-Software-EULA LCEDA-Distribution-License
sci-electronics/lceda-pro::gentoo-zh
- Ebuilds: 1, Testing: 3.2.186 Description:
Simple and efficient PCB design tools from China, free forever
Brand-new interactive routing engine, smooth and not stuck
Completely independent intellectual property rights, allowing you to focus on design with confidence
The EDA Tool of Choice for Next Generation Engineers
Homepage:https://lceda.cn/ License: LCEDA-Software-EULA LCEDA-Distribution-License
sci-electronics/liblxi::guru
- Ebuilds: 1, Testing: 1.20 Description:
liblxi is an open source software library which offers a simple API
for communicating with LXI compatible instruments. The API allows
applications to discover instruments on your network, send SCPI
commands, and receive responses.
Homepage:https://github.com/lxi-tools/liblxi License: BSD
librepcb (available in: sci-electronics/librepcb::gentoo, sci-electronics/librepcb::mva)
- Ebuilds: 2, Testing: 1.3.0, Snapshot: 9999 Description:
LibrePCB is a free EDA software to develop printed circuit boards.
Cross-platform, multilingual (both application and library elements), intuitive, modern and easy-to-use graphical user interface.
- All-In-One: project management + library/schematic/board editors
- Very powerful library design with some innovative concepts
- Human-readable file formats for both libraries and projects
- Multi-PCB feature (different PCB variants of the same schematic)
- Automatic netlist synchronisation between schematic and board
Homepage:https://librepcb.org/ License: GPL-3+
sci-electronics/lxi-tools::guru
- Ebuilds: 1, Testing: 2.7 Description:
lxi-tools are open source software tools for managing network attached LXI
compatible test instruments such as modern oscilloscopes, power supplies,
spectrum analyzers etc.
Features include automatic discovery of test instruments, sending SCPI
commands, grabbing screenshots from supported instruments, benchmarking
SCPI message performance, and powerful scripting for test automation. Both
a commandline tool and a GUI tool are available.
Homepage:https://github.com/lxi-tools/lxi-tools License: BSD
sci-electronics/magic::gentoo
- Ebuilds: 1, Stable: 8.3.365, Testing: 8.3.365 Description:
Magic is a venerable VLSI layout tool, written in the 1980's at Berkeley by
John Ousterhout, of Tcl fame. Due largely in part to its liberal Berkeley
open-source license, magic has remained popular with universities and small
companies. The open-source license has allowed VLSI engineers with a bent
toward programming to implement clever ideas and help magic stay abreast of
fabrication technology. However, it is the well thought-out core algorithms
which lend to magic the greatest part of its popularity. Magic is widely cited
as being the easiest tool to use for circuit layout, even for people who
ultimately rely on commercial tools for their product design flow.
Homepage:http://www.opencircuitdesign.com/magic/index.html License: HPND GPL-2+
sci-electronics/ngspice::gentoo
- Ebuilds: 2, Stable: 46, Testing: 46 Description:
Ngspice is a mixed-level/mixed-signal circuit simulator. Its code is based on
three open source software packages: Spice3f5, Cider1b1 and Xspice.
Homepage:https://ngspice.sourceforge.io/ License: BSD GPL-2 MPL-2.0
sci-electronics/nvc::gentoo
- Ebuilds: 3, Stable: 1.22.0, Testing: 1.22.1 Description:
NVC is a VHDL compiler and simulator. NVC supports almost all of VHDL-2008
with the exception of PSL, and it has been successfully used to simulate
several real-world designs. Experimental support for VHDL-2019 is under
development. NVC has a particular emphasis on simulation performance and
uses LLVM to compile VHDL to native machine code. NVC is not a synthesizer.
That is, it does not output something that could be used to program an FPGA
or ASIC. It implements only the simulation behaviour of the language as
described by the IEEE 1076 standard. NVC supports popular verification
frameworks including OSVVM, UVVM, and VUnit.
Homepage:https://www.nickg.me.uk/nvc/
https://github.com/nickg/nvc/ License: GPL-3+
sci-electronics/openboardview-bin::guru
- Ebuilds: 1, Testing: 10.0.0 Description:
OpenBoardView is a Linux SDL/ImGui edition software for viewing .brd files.
Intended as a drop-in replacement for the "Test_Link" software and "Landrex".
Homepage:https://openboardview.org License: MIT
sci-electronics/openems::vowstar
- Ebuilds: 1, Testing: 0.0.36 Description:
openEMS is a free and open electromagnetic field solver using the
FDTD method. It supports Cartesian and cylindrical coordinates,
multi-threading via OpenMP, SIMD acceleration, and a Matlab/Octave
scripting interface for setting up simulations.
Homepage:https://openems.de https://github.com/thliebig/openEMS License: GPL-3
sci-electronics/opensta::vowstar
- Ebuilds: 1, Testing: 2.7.0_pre20251212 Description:
OpenSTA is a gate level static timing verifier. As a stand-alone
executable it can be used to verify the timing of a design using
standard file formats. OpenSTA uses a TCL command interpreter to
read the design, specify timing constraints and print timing reports.
Homepage:https://github.com/parallaxsw/OpenSTA License: GPL-3
sci-electronics/petrify::gentoo
- Ebuilds: 1, Testing: 4.2 Description:
Petrify is a tool for synthesis of Petri nets and asynchronous controllers.
Petrify is able to obtain Petri nets with some specific properties: pure, free
choice, unique choice, place irredundant, etc... The Petri nets accepted by
petrify can also be interpreted as Signal Transition Graphs describing the
behavior of asynchronous controllers. Petrify is able to solve the Complete
State Coding problem and generate a speed-independent circuit.
Homepage:http://www.lsi.upc.edu/~jordicf/petrify/ License: Old-MIT
sci-electronics/plecs-bin::vowstar
- Ebuilds: 1, Testing: 5.0.3 Description:
PLECS Standalone is a block diagram simulator developed by Plexim
for high-speed simulations of power electronic circuits and
electrical systems. It combines an intuitive schematic editor
with a powerful simulation engine and provides specialized
libraries for power semiconductors, electrical machines, thermal
modeling and control. This package installs the proprietary
Linux 64-bit binary distribution; a valid license from Plexim is
required at runtime.
Homepage:https://www.plexim.com/products/plecs/plecs_standalone License: Plexim-EULA
sby (available in: sci-electronics/sby::guru, sci-electronics/sby::vowstar)
- Ebuilds: 3, Testing: 0.69 Description:
SymbiYosys (sby) is a front-end driver program for Yosys-based formal
hardware verification flows. It supports bounded model checking (BMC),
unbounded model checking, and cover property checking for hardware
designs written in Verilog, SystemVerilog, or VHDL. SymbiYosys
integrates with various SMT solvers and model checkers including
Yices, Z3, Boolector, and ABC.
Homepage:https://github.com/YosysHQ/sby License: ISC
slang (available in: sci-electronics/slang::guru, sci-electronics/slang::vowstar)
- Ebuilds: 4, Testing: 11.0, Snapshot: 9999 Description:
slang is a software library that provides various components for lexing,
parsing, type checking, and elaborating SystemVerilog code. It comes with
an executable tool that can compile and lint any SystemVerilog project,
but it is also intended to be usable as a front end for synthesis tools,
simulators, linters, code editors, and refactoring tools.
slang is the fastest and most compliant SystemVerilog frontend
(according to the open source chipsalliance test suite).
Homepage:
https://sv-lang.com
https://github.com/MikePopoloski/slang
License: MIT
sci-electronics/smuview::sinustrom
- Ebuilds: 1, Snapshot: 9999 Description:
SmuView (sometimes abbreviated as "SV") is a Qt based GUI for power
supplies, electronic loads and all sorts of measurement devices like
multimeters, LCR meters, scales and so on.
Homepage:https://github.com/knarfS/smuview License: GPL-3
sci-electronics/spice::gentoo
- Ebuilds: 1, Stable: 3.5.5, Testing: 3.5.5 Description:
SPICE is a general-purpose circuit simulation program for nonlinear dc,
nonlinear transient, and linear ac analyses. Circuits may contain resistors,
capacitors, inductors, mutual inductors, independent voltage and current
sources, four types of dependent sources, lossless and lossy transmission
lines (two separate implementations), switches, uniform distributed RC lines,
and the five most common semiconductor devices: diodes, BJTs, JFETs, MESFETs,
and MOSFETs.
Homepage:http://bwrcs.EECS.Berkeley.EDU/Classes/IcBook/SPICE/ License: BSD
sci-electronics/splat::gentoo
- Ebuilds: 2, Testing: 1.4.2 Description:
SPLAT! is an RF Signal Propagation, Loss, And Terrain analysis tool for the
spectrum between 20 MHz and 20 GHz. Applications of SPLAT! include site
engineering, wireless network design, amateur radio communications, frequency
coordination, communication system design, and terrestrial television and radio
broadcasting.
Homepage:https://www.qsl.net/kd2bd/splat.html License: GPL-2
surfer (available in: sci-electronics/surfer::guru, sci-electronics/surfer::vowstar)
- Ebuilds: 2, Testing: 0.7.0 Description:
Surfer is a waveform viewer with a focus on a snappy usable interface,
and support for many waveform formats. It can be used to view waveforms
from digital design simulations (VCD, FST, GHW) and supports features
like signal search, markers, and annotations. Surfer also includes a
server component (surver) for remote waveform viewing.
Homepage:https://surfer-project.org/ https://gitlab.com/surfer-project/surfer License: EUPL-1.2
0BSD Apache-2.0 Apache-2.0-with-LLVM-exceptions BSD Boost-1.0
CC0-1.0 CDLA-Permissive-2.0 EUPL-1.2 ISC MIT MPL-2.0 OFL-1.1
UbuntuFontLicense-1.0 Unicode-3.0 ZLIB
systemc (available in: sci-electronics/systemc::gentoo, sci-electronics/systemc::vowstar)
- Ebuilds: 4, Stable: 3.0.2, Testing: 3.0.2 Description:
SystemC provides hardware-oriented constructs within the context of C++
as a class library implemented in standard C++. Its use spans design and
verification from concept to implementation in hardware and software.
SystemC provides an interoperable modeling platform which enables the
development and exchange of very fast system-level C++ models. It also
provides a stable platform for development of system-level tools.
Homepage:
https://systemc.org
https://github.com/accellera-official/systemc
License: Apache-2.0
sci-electronics/topola::vowstar
- Ebuilds: 1, Testing: 0.1.0_pre20251201 Description:
Topola is a work-in-progress interactive topological router for printed
circuit boards (PCBs) written in Rust. It implements rubberband-style
routing where traces behave like elastic bands wrapped around obstacles,
providing an intuitive way to route PCB traces interactively. The project
aims to provide both interactive routing and autorouting capabilities for
PCB design workflows.
Homepage:https://topola.dev https://codeberg.org/topola/topola License: MIT
Apache-2.0 Apache-2.0-with-LLVM-exceptions Boost-1.0 CC0-1.0 ISC MIT
MPL-2.0 OFL-1.1 UbuntuFontLicense-1.0 Unicode-3.0 ZLIB
vcd (available in: sci-electronics/vcd::guru, sci-electronics/vcd::vowstar)
- Ebuilds: 2, Testing: 221217 Description:
The VCD (Value Change Dump) project on GitHub is a command line viewer
for VCD files, compatible with Windows, Linux, and MacOS.
It enables users to view and analyze waveform data from digital
simulations. The tool provides customization options for waveform
display and supports various output formats including YAML.
Installation is available via prebuilt binaries, source compilation, or
package managers.
The project is actively maintained and includes sample files and
detailed usage instructions. The repository is licensed under MIT and
supports CLI operations for efficient waveform analysis.
Homepage:https://github.com/yne/vcd License: MIT
sci-electronics/verible::vowstar
- Ebuilds: 3, Testing: 0.0.3644 Description:
Verible is a suite of SystemVerilog developer tools, including a parser,
style-linter, and formatter.
The Verible project's main mission is to parse SystemVerilog
(IEEE 1800-2017) (as standardized in the SV-LRM) for a wide variety of
applications, including developer tools.
It was born out of a need to parse un-preprocessed source files, which is
suitable for single-file applications like style-linting and formatting.
In doing so, it can be adapted to parse preprocessed source files, which is
what real compilers and toolchains require.
The spirit of the project is that no-one should ever have to develop a
SystemVerilog parser for their own application, because developing a
standard-compliant parser is an enormous task due to the syntactic
complexity of the language. Verible's parser is also regularly tested
against an ever-growing suite of (tool-independent) language compliance
tests at https://symbiflow.github.io/sv-tests/.
A lesser (but notable) objective is that the language-agnostic components
of Verible be usable for rapidly developing language support tools for
other languages.
Homepage:
https://chipsalliance.github.io/verible/
https://github.com/chipsalliance/verible
License: Apache-2.0
sci-electronics/wavedrom-editor-bin::vowstar
- Ebuilds: 1, Testing: 2.9.1 Description:
WaveDromEditor is real-time editor of digital timing diagrams based on
WaveDrom engine and WaveJSON format. WaveDrom draws your Timing Diagram
or Waveform from simple textual description.
It comes with description language, rendering engine and the editor.
WaveDrom editor works in the browser or can be installed on your system.
Rendering engine can be embeded into any webpage.
Homepage:
https://wavedrom.com
https://github.com/wavedrom/wavedrom.github.io
License: MIT
sci-electronics/xcircuit::gentoo
- Ebuilds: 1, Stable: 3.10.30, Testing: 3.10.30 Description:
XCircuit is a UNIX/X11 program for drawing publishable-quality electrical
circuit schematic diagrams and related figures, and produce circuit netlists
through schematic capture. XCircuit regards circuits as inherently
hierarchical, and writes both hierarchical PostScript output and hierarchical
SPICE netlists. Circuit components are saved in and retrieved from libraries
which are fully editable. XCircuit does not separate artistic expression from
circuit drawing; it maintains flexiblity in style without compromising the
power of schematic capture.
Homepage:http://opencircuitdesign.com/xcircuit License: GPL-2
sci-electronics/xnec2c::gentoo
- Ebuilds: 1, Stable: 4.4.18, Testing: 4.4.18 Description:
xnec2c is a GTK+ graphical interactive version of nec2c. It incorporates
the nec2c core which it uses for reading input files and calculating
output data, but it does not need and indeed does not produce an output
file by default. Since xnec2c incorporates the nec2c core, it has access
to all internal buffers, including structure data, frequency-related
data (structure currents, input impedance, gain etc) and radiation
pattern data (for the far field and near field). It therefore has the
ability to graphically display user-requested data directly, as the
frequency loop progresses or after input from the user. Graphs of
frequency-related data and the current or charge distribution evolve as
the frequency loop progresses, and radiation patterns (far and near
field) are sequentially drawn for each frequency step. A new frequency
can be entered by the user from spin buttons in the main or radiation
pattern windows or by clicking on the graphs of frequency-related data.
New output data are then computed and displayed in text and graphical
form.
Homepage:https://www.xnec2c.org License: GPL-2
yosys (available in: sci-electronics/yosys::guru, sci-electronics/yosys::qsx, sci-electronics/yosys::salfter, sci-electronics/yosys::vowstar, sci-electronics/yosys::xdch47)
- Ebuilds: 6, Testing: 0.69 Description:
This is a framework for RTL synthesis tools. It currently has extensive
Verilog-2005 support and provides a basic set of synthesis algorithms
for various application domains.
Yosys can be adapted to perform any synthesis job by combining the
existing passes (algorithms) using synthesis scripts and adding
additional passes as needed by extending the yosys C++ code base.
Yosys is free software licensed under the ISC license (a GPL compatible
license that is similar in terms to the MIT license or the 2-clause BSD
license).
Homepage:https://yosyshq.net/yosys/ License: ISC